ASIC/SOC Silicon Physical Design Engineer (Mountain View) Job at MatX, Mountain View, CA

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  • MatX
  • Mountain View, CA

Job Description

ASIC/SOC Silicon Physical Design Engineer

Join to apply for the ASIC/SOC Silicon Physical Design Engineer role at MatX

ASIC/SOC Silicon Physical Design Engineer

Join to apply for the ASIC/SOC Silicon Physical Design Engineer role at MatX

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MatX's mission is to make the world's best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability. MatX is seeking silicon physical design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Silicon Physical Design Engineers will be responsible for developing performant and functionally correct silicon for MatX products across compute, memory management, high-speed connectivity, and other key technologies in leading-edge process nodes.

Responsibilities include:

  • Contribute to MatX's Physical Design methodology to achieve a scalable solution across block, subsystem, and fullchip designs from RTL to GDSII
  • Own entire subsystems or subsets and/or chip-level Physical Design deliverables including but not limited to: construction (partitioning, floorplanning, synthesis, place & route, clocking) and sign-off (equivalency, extraction, timing, power estimation, EMIR, physical verification)
  • Plan and drive intermediate and sign-off reviews. Report execution progress towards various silicon milestones including design freeze and tapeout
  • Work closely with the Design, DFT, and other Physical Design co-owners of the subsystem/block in question to deliver best-in-class Performance-Power-Area results

Requirements:

  • Bachelor of Science in Electrical Engineering or equivalent
  • Minimum 8 years of industry experience in ASIC Physical Design
  • Great interpersonal and communication skills
  • Strong proficiency in programming languages such as Perl, Python, and TCL
  • Expertise driving Physical Design construction and sign-off for blocks, subsystems, and/or fullchip from early RTL to production silicon
  • Experience collaborating with Design, Verification, and DFT teams to structure, partition, and optimize designs for PPA through sign-off

Preferred Experience:

  • 8 years of industry experience in ASIC Physical Design
  • Experience working with third-party Design Services partners

Compensation

  • The US base salary for this full-time position is $120,000 - $400,000 + equity

Benefits

  • Commuter stipend available for employees within 60 minutes of the office
  • 401(k) with contribution matching
  • Health, vision, and dental insurance
  • Life and AD&D insurance

As part of our dedication to the diversity of our team and our focus on creating an inviting and inclusive work experience, MatX is committed to a policy of Equal Employment Opportunity and will not discriminate against an applicant or employee on the basis of race, color, religion, creed, national origin or ancestry, sex, gender, gender identity, gender expression, sexual orientation, age, physical or mental disability, medical condition, marital/domestic partner status, military and veteran status, genetic information or any other legally recognized protected basis under federal, state or local laws, regulations or ordinances.

All candidates must be authorized to work in the United States and work from our offices in Mountain View Tuesdays-Thursdays.

This position requires access to information that is subject to U.S. export controls. This offer of employment is contingent upon the applicants capacity to perform job functions in compliance with U.S. export control laws without obtaining a license from U.S. export control authorities.

MatX does not accept unsolicited resumes from individual recruiters or third-party recruiting agencies in response to job postings. No fee will be paid to third parties who submit unsolicited candidates directly to our hiring managers or People team and any resumes submitted are deemed to be the property of MatX.

Seniority level

  • Seniority level

    Mid-Senior level

Employment type

  • Employment type

    Full-time

Job function

  • Job function

    Engineering and Information Technology

  • Industries

    Computer Hardware Manufacturing

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Job Tags

Full time, Work experience placement, Work at office, Local area,

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Job Summary
  • Location
    Mountain View, CA
  • Job Type
    Full Time
  • Date Posted
    2025-08-14
  • Expiration date
    2025-09-13