Primary Skill: Python Programming Language Responsibilities: Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, floor-plan, place & route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes. Resolve design and flow issues related to physical design, identify potential solutions, and drive execution. Deliver physical design of an end-to-end IP or integration of ASIC/SoC design. Qualifications: 0-1 years of experience as an Engineer – CL11 & CL10. Master's degree in Electrical Engineering or Computer Science. RTL to GDSII experience on advanced technology nodes (7nm and below). Experience with low power implementation and signoff, power gating, multiple voltage rails, UPF/CPF knowledge. Experience in block-level and full-chip floor-planning and power grid planning, with Python, TCL, or Perl programming, working with EDA tools like DC/Genus, ICC2/Innovus, Primetime, Redhawk/Voltus, or Calibre. Additional Job Details: Hardware Troubleshooting (P1 - Beginner) Product Verification & Validation (P1 - Beginner) Quality Engineering Strategy and Planning (P1 - Beginner) #J-18808-Ljbffr
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